Sulla sintesi di reti NAND o nor a molti livelli

Abstract

Some authors have proved that a minimal two-level NAND or NOR network can be obtained by the convetional procedures for determining minimal normal forms. But when either the complements of some input variables are not available or the gates have a limited number of inputs, the two-level synthesis is generally impossible; and no procedure has been described for the minimal sunthesis of networks having more than two levels of gates. In this paper some new procedures are described for the synthesis of NAND or NOR networks having more than two levels of gates. In the first sections the properties are briefly described, by which a NAND or NOR expression is equivalent to a conventional expression containing only the AND and OR operators; also, the problem of determining a minimal two-level NAND or NOR network is summarized. Then the synthesis of three-level NAND or NOR networks is considered, in case that both the true and complemented values of input variables are available, and the gates can have an unlimited number of inputs (condition 1). A new procedure is described which makes it possible to find one of the minimal NAND or NOR networks, having a tree-shaped structure, and which gives also quasi-minimal solutions for the general case in which the output of a gate can be connected to the inputs of more than one gate of the next level. The procedure derives from the methods described in a preceding paper by the present author for determining the minimal «sums of products of sums» of an assigned function; but some properties and the particular definition of cost make it possible to apply a computation technique, which simplifies this problem considerably. Then the synthesis problem is considered when the gates can have an unlimited number of inputs but the complements of some of the input variables are not available (condition 2). In this case the two-level synthesis is generally impossible (a simple necessary and sufficient condition for a two-level solution to exist is proved); on the contrary, a three-level NAND or NOR network always exists, which implements the assigned function. This network can be determined with the procedure which has been described for determining the minimal three-level networks in condition 1, but the new conditions simplify the problem and a remarkable reduction of the computation work is possible. Lastly the following cases are considered: In these cases a two- or a three-level synthesis may be impossible, but one can always verify whether a two- or a three-level network implementing the assigned function exists. However a simple procedure is described, which always makes it possible to find a quasi-minimal solution characterized by more than three levels of gates.