Abstract
This paper investigates the impact of gate length scaling on the performance of junctionless (JL) and metal-ferroelectnc-metalinsulator-semiconductor (MFMIS) JL transistors. While the performance of JL transistor degrades significantly at gate length of 15 nm due to higher off-current $(I_{\mathrm{o}\mathrm{f}\mathrm{f}})$, MFMIS JL device can be turned-off with significantly lower $I_{\mathrm{o}\mathrm{f}\mathrm{f}}$. The performance of MFMIS JL transistor has been compared with inversion mode (IM) device, and result showcases that MFMIS JL transistor exhibits lower $I_{\mathrm{o}\mathrm{f}\mathrm{f}}$ and higher on-to-off current ratio $(I_{\mathrm{o}\mathrm{n}}/I_{\mathrm{o}\mathrm{f}\mathrm{f}})$ than MFMIS IM transistor. We analyzed the influence of drain bias and spacer properties on the performance of MFMIS JL and IM devices. Our results show that MFMIS JL transistor with higher $I_{\mathrm{o}\mathrm{n}}/I_{\mathrm{o}\mathrm{f}\mathrm{f}}$ exhibits better scalability than MFMIS IM transistor for low power applications.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Similar Papers
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.