Subthreshold analog/RF performance of underlap DG FETs with asymmetric source/drain extensions

Abstract

DG FETs with underlap architectures exhibit better performance for logic applications owing to its improved immunity to short channel effects. In this work, we have analyzed the effect of symmetric and asymmetric source drain extensions in the underlap DG FETs for improved subthreshold analog and RF performance in the 45nm gate length regime. The various figures of merits such as transconductance, transconductance generation factor and intrinsic gain along with cut-off frequency, maximum frequency of oscillation and gain–bandwidth product are investigated for symmetric and asymmetric drain extensions in the underlapped DG FETs. The underlap length of the asymmetric DG FETs is also varied for improved device performance parameters. For circuit analysis, a cascode amplifier is analyzed for higher gain by biasing the load transistor with the special importance in the subthreshold regime as CMOS circuits operated in this regime are very much attractive for ultralow-power high gain performances. For AC analysis, the gain–frequency curve of a common source amplifier is studied for the improved gain–bandwidth product and an improvement of about 55% was observed in the asymmetric DG underlap devices compared to its symmetric counterpart.