Substrate-Voltage Modulation of Currents in Symmetric SOI Lateral Bipolar Transistors

Abstract

The modulation of the currents in a symmetric Semiconductor-on-Insulator (SOI) lateral bipolar transistor with a voltage applied to the SOI substrate is studied. For an n-p-n transistor, a positive substrate bias could greatly increase the collector current, especially at low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BE</sub> values, while having relatively little effect on the base current. Similarly, a negative substrate bias could greatly increase the collector current of a p-n-p transistor. The physical mechanisms responsible for the modulation effects are discussed. The potential of using substrate bias to enhance the performance of symmetric SOI lateral bipolar circuits is briefly discussed.