Substrate Induced Overlay Non-Uniformity Study

Abstract

According to ITRS roadmap, the overlay control becomes more and more critical with the layout design shrinkage. In order to meet the tight overlay requirement lots of new techniques had been proposed from exposure system, metrology equipment and APC algorithm. Although current overlay techniques can obviously improve overlay control capability, they still cannot include all factors which will impact overlay into the model. To describe the impact from those factors which are not involved in model, the model fitting error is introduced. Normally it is not so important in generic logical process. But it will become very serious and lead to terrible yield loss in some special case. In all kinds of factors which impact to overlay, the wafer substrate and thermal process are seldom reported, but actually both of them are critical or fatal factors of overlay fail in high voltage and high power devices which have lots of high temperature thermal process. In this paper, we will demonstrate the overlay non-uniformity study with different substrates, film stacks, thermal processes and EPI processes. Seriously random occurrence of overlay non-uniformity is found and the model fitting error is very large. It cannot be resolved by typical overlay improvement method such as overlay mark design, alignment detecting, overlay metrology method and APC algorithm refine. Splits on wafer substrate, thermal and EPI process are proposed. Finally the non-uniformity is reduced by over 90% and model fitting error is also largely reduced.