Substrate Design Optimization of Fine Pitch FCCSP for Molded Underfill Void Free Evaluation

Abstract

The microelectronics products of Flip Chip-Chip Scale Package (FCCSP) with more increasing challenges are faced to assure molding capability with rapid advances in flip chip technology such as decreasing stand-off height and fine bump pitch (high bump density), especially when Molded Underfill (MUF) is used during transfer molding process. There is one important challenge that faced severe air void entrapment underneath the die region (air void concentrate among bumps region). Generally, the experiments involving a lot of DOE matrixes which spend a lot of time and materials (dummy die, substrate, mold compound…etc.) to solve this air void issue. As above reasons, the moldflow simulation can be used to apply molding parameters to find out optimum solutions for air void risk free of MUF FCCSP with different substrate solder mask pattern design which can reduce development cycle time before mass production. In this paper, 3D moldflow simulation software which can apply transfer molding process parameters is used. There is substrate solder mask with different opening area percentage (finger like) design within die region and molding compound flow to die region that solder mask opening area with 20um depth structure to perform different melt-front behavior. From this study, we can conclude some results for improvement molding performance of FCCSP(MUF) during transfer molding process. The FCCSP(MUF) with the 65um stand-off height structure performs low air void risk due to mold compound could easily flow under die region with more flow space. In addition, mold compound also performs well melt-front flow when the substrate solder mask with opening area as 25% and opening pattern design as horizontal as flow direction that both can get more space and smooth flow underneath die region to reduce void risk during molding process.