Substrate BOX engineering to mitigate the self-heating induced degradation in nanosheet transistor

Abstract

The continued scaling of 3D transistors into the ultra-scaled-down nanoscale regime causes self-heating effect (SHE) driven thermal deterioration. Particularly in silicon-on-insulator (SOI) FETs, the induced thermal degradation is more severe due to the presence of a conventional lower thermal conductivity material (i.e., SiO2) as a buried oxide (BOX), which obstruct the heat flow from the active area to substrate. Thus, the lattice temperature rises above the ambient temperature. Therefore, in this paper, we proposed a substrate-BOX engineered Nanosheet (BOXNS) FET to mitigate the self-heating-induced thermal degradation. Through well-calibrated TCAD models, we investigated the impact of incorporating a superior dielectric material with significantly higher thermal conductivity, such as crystalline diamond (kth = 2000 W m−1 K−1) in place of conventional SiO2, possessing lower thermal conductivity (kth = 1.4 W m−1 K−1) beneath the source and drain region. The results reveal that the proposed BOXNS FET effectively improves the SHE-induced thermal degradation in terms of ON current (ION), OFF current (IOFF), effective thermal resistance (Reff), and lattice temperature (Tlattice), compared to the conventional SiO2 Nanosheet (SiONS) FET. In BOXNS, the hotspots from the active (channel) region find a pathway through the realized crystalline diamond (DLC) and thus decreases the lattice temperature by 13.5 K. Moreover, the dimensional variation, such as channel thickness variation in the proposed BOXNS FET, shows less effective thermal resistance and lattice temperature fluctuations than the SiONS FET while varying the ambient temperature from 300 K to 370 K.