Sub-sampling PLL techniques

Abstract

The phase-locked-loop (PLL) is a ubiquitous component in modern ICs due to its versatility. It can, for instance, be used for clock generation, frequency synthesis, frequency modulation and demodulation, clock and data recovery, synchronization, and spread spectrum signal generation, in applications like high-performance analog-to-digital converters, wireline and optical transceivers, and wireless radio transceivers. Of the many known PLL architectures, the one shown in Figure 21.1(a) is perhaps the most widely used which we call the "classical PLL" architecture. It consists of a voltage -controlled oscillator (VCO) locked to a reference clock Ref by a feedback loop with the following "loop components": a phase detector (PD), a charge pump (CP), a loop filter (LF), and a frequency divider with ratio N (÷N). Jitter (or phase noise) and power are often the two critical performance matrix for many PLL applications. With the trend of higher data -rate, higher carrier frequency and higher order of modulation, the jitter or phase noise requirement becomes more and more demanding while the power budget is still limited. The PLL's jitter performance for a given power can be evaluated with the PLL jitter and power figure-of-merit (FOM) [1]. In the classical PLL, the PD and CP noise is multiplied by N2 and often dominates the in -band phase noise, thus limiting the achievable PLL FOM.