Sub-quarter-micrometer CMOS on ultrathin (400 AA) SOI

Abstract

MOS transistors with effective channel lengths down to 0.2 mu m have been fabricated in fully depleted, ultrathin (400 AA) silicon-on-insulator (SOI) films. These devices do not exhibit punchthrough, even for the smallest channel lengths, and have performance characteristics comparable to deep-submicrometer bulk transistors. The NMOS devices have a p/sup +/-polysilicon gate, and the PMOS devices have an n/sup +/-polysilicon gate, giving threshold voltages close to 1 V with very light channel doping. Because the series resistance associated with the source and drain regions can be very high in such thin SOI films, a titanium salicide process was used using a 0.25 mu m oxide spacer. With this process, the sheet resistance of the silicided SOI layer is approximately 5 Omega / Square Operator . However, the devices still exhibit significant series resistance, which is likely due to contact resistance between the silicide and silicon source/drain regions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>