Abstract
Fabrication procedure and yield analysis of superconducting integrated receivers is reported. These chip receivers, apart from the quasi-optical SIS mixers, contain internal local oscillators and associated rf and dc interfaces. Due to both complexity and design requirements of the integrated circuit, certain restrictions are applied to the standard Nb/Al/Al/sub x/O/sub y//Nb SNEAP process. To obtain accurate area for micron-size SIS junctions and thickness for multi-layer SiO/sub 2/ insulation, a few solutions and modifications were developed. The possibility of transferring this fabrication process worldwide has been proven experimentally.
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