Abstract
High-speed low-noise clocks are essential in numerous applications. In this paper, complete analysis and validation of subharmonic injection locking that can substantially reduce the PLL phase noise at negligible cost is presented. Two 20 GHz PLLs based on this technique demonstrate 149 and 85 fs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> jitter while consuming 38 and 105mW, respectively.
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