Sub-harmonic oscillations attenuation in hardware-in-the-loop models using the Integration Oversampling Method

Abstract

Hardware-in-the-loop (HIL) technology has become widespread for testing purposes, gaining special importance in micro-grids and renewable energy. One of the main challenges in HIL technology is its use in mid or high-frequency applications. In those cases, oversampling gate signals is a must to obtain enough accuracy and avoid undesirable sub-harmonic oscillations in the emulation that would not appear in a real scenario or offline electrical simulation. However, handling the extra information obtained through oversampling increases significantly the complexity of switched models since the oversampling methods deal with more than one sample per simulation step. It leads to extra design effort if the models are designed ad-hoc or increased hardware resources when using vendor tools that implement oversampling techniques. In both cases, oversampling traditionally implies an increase in the overall cost of the HIL system. This paper proposes the Integration Oversampling Method (IOM), which manages the extra information obtained through oversampling with a minimum impact on the models’ complexity. In fact, the power model is not changed at all and uses just one switch state per simulation step. The method consists in adding a small hardware block in the input of the gate signals. Using the additional information obtained through oversampling, it generates a set of switch states in every simulation step that minimizes the integrated error in the input reading. The experimental results obtained through an NI myRIO device show clearly enhanced performance when using IOM both in transient and steady-state operation. At the same time, the additional hardware resources necessary for IOM implementation are negligible.