Sub-Boltzmann transistors with piezoelectric gate barriers

Abstract

Scaling of field-effect transistors (FETs) is limited by the high power dissipation density, and the resulting heat generation in ICs [1]. This is due to the non-scalability of subthreshold slope (SS), i.e. the gate voltage required to change the drain current by an order of magnitude; the value is limited to SS=kTln(10)~60 mV/dec in a classical Boltzmann FET switch [2-3]. Tunneling FETs are being investigated for sub-Boltzmann switching. But even a conventional FET can potentially achieve sub-Boltzmann switching taking advantage of ferroelectric gates materials [3]. It is possible to amplify the internal channel surface potential, Ψs over the applied gate bias voltage, Vg; using negative differential capacitance (NDC) in the gate insulator. The “body factor” then reduces below unity i.e. m = ∂Vg / ∂Ψs <; 1, and hence the subthreshold slope (SS=m×60 mV/dec) can be lowered below 60 mV/dec. In this work, we show that such internal gain mechanism can also exist in piezoelectric gate materials, such as in AIN/GaN heterostructures.