Sub-100 nm Gate III-V MOSFET for Digital Applications

Abstract

The performance of nano-CMOS digital ICs is characterized in terms of key figure of merits, which provides a benchmark for III-V compound semiconductor MOSFETs. The selection of III-V channel material is discussed based on the transport properties, i.e., the intrinsic electron mobility and hole mobility, of different III-V alloys. To improve the hole mobility for III-V p-MOSFETs, the effects of strain-induced hole mobility enhancement are reviewed. Critical process issues for self-aligned III-V MOSFET are thermal stability of the oxide-semiconductor interface and source/drain doping limitations. The advantages of self-aligned GaAs enhancement-mode MOSFETs using regrown source and drain regions are demonstrated. Finally, the state-of-the-art device performance of sub-100 nm gate III-V FETs is compared with Si MOSFETs.