Sub-threshold, cascode compensated, bulk-driven OTAs with enhanced gain and phase-margin

Abstract

This paper presents sub-threshold, bulk-driven two-stage cascode compensated operational transconductor, which drive load up to 60pF. The input core in the first stage uses a bulk-driven source-degenerated, gate-regenerated class AB flipped voltage follower (FVF), which ensures rail-to-rail linear input signal drive capability in its unity gain configuration. The self-cascode load of input stage followed by a common source (CS) second stage having simple current source load, have enhanced overall gain around 100dB at 1mHz. Instead of Miller compensation, cascode compensation has been implemented by using two capacitors (CC/2) each of value 4pF in this OTA. It has increased its phase margin and gain bandwidth as compared to Miller compensation, under identical load and total compensation capacitors. It ensured better rail-to-rail linearity (THD <−44dB) at 200Hz frequency consuming around 74nW power from ±250mV dual power supply.Another three-stage OTA is also proposed, which includes one additional CS class AB buffer at the output of OTA1, to drive R–C shunt load. This buffered OTA is additionally nested Miller compensated using capacitor (CNMC) of 0.2pF. This buffering enhances slew rate and gain bandwidth (GBW) by two-times as compared to un-buffered structure at the cost of power.The Cadence VIRTUOSO environment using UMC 0.18µm CMOS process technology has been used to simulate the proposed circuits.