Sub-nm equivalent oxide thickness on Si-passivated GaAs capacitors with low Dit

Abstract

A thin amorphous silicon interlayer, inserted between the III-V semiconductor and the gate dielectric is expected to prevent III-V oxidation, as required for high-mobility channel transistors. We demonstrate that the addition of a thin Al2O3 barrier layer between the a-Si and the high-k HfO2, together with optimized post-metallization annealing, is the key to reduce the a-Si consumption and to achieve a highly scaled gate stack with equivalent oxide thickness of ∼0.8 nm. The evolution of the interfaces during growth and the quality of the stack are investigated by in-situ X-ray photoelectron spectroscopy and electrical measurements on metal-oxide-semiconductors capacitors.