Sub-60-nm Extremely Thin Body ${\rm In}_{x}{\rm Ga}_{1-x}{\rm As}$-On-Insulator MOSFETs on Si With Ni-InGaAs Metal S/D and MOS Interface Buffer Engineering and Its Scalability

Abstract

We report the operation of sub-60-nm deeply scaled InGaAs- and InAs-on-insulator (-OI) MOSFETs on Si substrates with MOS interface buffer engineering and Ni-InGaAs metal source/drain (S/D). InAs-OI MOSFETs provide 400% Ion enhancement, compared with an In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As control device with the same drain-induced-barrier-lowering (DIBL) of 100 mV/V, which is attributable to the mobility enhancement and the S/D parasitic resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SD</sub> ) reduction. In addition, InAs-OI MOSFETs with the MOS interface buffers show excellent electrostatic characteristics. InAs-OI MOSFETs with a channel length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</sub> ) of 55 nm shows small DIBL of 84 mV/V and subthreshold slope (S.S.) of 105 mV/dec, both of which do not significantly degrade with a decrease of L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</sub> , thanks to the extremely thin channel thickness. In addition, from the simulation study, we have found that further vertical scaling and back biasing techniques can improve the control of short channel effect in InAs-OI MOSFETs.