Sub-15 nm Silicon Lines Fabrication via PS-b-PDMS Block Copolymer Lithography

Sozaraj Rasappa,Lars Schulte,Dipu Borah,Michael A Morris,Sokol Ndoni

doi:10.1155/2013/831274

Abstract

This paper describes the fabrication of nanodimensioned silicon structures on silicon wafers from thin films of a poly(styrene)-block-poly(dimethylsiloxane) (PS-b-PDMS) block copolymer (BCP) precursor self-assembling into cylindrical morphology in the bulk. The structure alignment of the PS-b-PDMS (33 k–17 k) was conditioned by applying solvent and solvothermal annealing techniques. BCP nanopatterns formed after the annealing process have been confirmed by scanning electron microscope (SEM) after removal of upper PDMS wetting layer by plasma etching. Silicon nanostructures were obtained by subsequent plasma etching to the underlying substrate by an anisotropic dry etching process. SEM images reveal the formation of silicon nanostructures, notably of sub-15 nm dimensions.

Highlights

Continuing miniaturisation of microelectronics and nanoelectronics devices strongly demands controlled high density nanodimensioned structures in wafer scale [1,2,3,4]
This paper describes the fabrication of nanodimensioned silicon structures on silicon wafers from thin films of a poly(styrene)block-poly(dimethylsiloxane) (PS-b-PDMS) block copolymer (BCP) precursor self-assembling into cylindrical morphology in the bulk
The upper PDMS layer formed during self-assembly has been removed by using CF4 and O2 plasma for 15 s after which the nanopatterns became clearly visible in the scanning electron microscope (SEM) images (Figures 1(a)–1(h))

Summary

Introduction

Continuing miniaturisation of microelectronics and nanoelectronics devices strongly demands controlled high density nanodimensioned structures in wafer scale [1,2,3,4]. Feature size reduction is conventionally achieved following the usage of UV, e-beam, and X-ray lithographic processes, for obtaining sub-22 nm device structures [5] These topdown methodologies of device fabrication are already well established in silicon industries for chip miniaturisation in large scale [6]. Alternative intrinsically parallel methodologies based on bottom-up approaches that exploit block copolymer (BCP) self-assembly as nanostructure generator are becoming increasingly attractive among researchers [9]. The potential of such approaches is to generate predictable sub-10 nm structures at low costs [10, 11]. Challenges exist in getting highly packed device features [15] generated through BCPs

Methods

Results

Conclusion