Sub‐100 nm gate‐length SiGe/Si MIS‐HFET using Cat‐CVD SiN

Abstract

AbstractWe fabricated sub‐100 nm gate‐length SiGe/Si n‐channel metal‐insulator‐semiconductor (MIS) heterostructure field‐effect transistors (HFETs) using a SiN gate insulator formed by catalytic chemical vapor deposition (Cat‐CVD). The Cat‐CVD SiN thin film (5 nm) was found to be an effective gate insulator with good gate controllability and dielectric properties. Due to the MIS structure, large gate bias swing was achieved from ‐3 to 3 V, and the maximum drain current density exceeded 450 mA/mm. The maximum transconductance (gm) was 220 mS/mm at VGS = 3 V, which was larger than that for a Schottky‐gate device. RF measurements of the MIS‐gate device, however, showed a relatively lower current gain cutoff frequency (fT) compared with the Schottky‐gate device, suggesting that two electron transport channels existed for the MIS‐gate structure, one at the SiGe/Si buried channel and the other at the SiN/Si surface channel. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)