Abstract
Advancements in semiconductor technology are making gate-level test generation more challenging. This is because a large amount of detailed structural information must be processed in the search process of automatic test pattern generation (ATPG). In addition, ATPG needs to deal with new defects caused by process variation when IC is shrinking. To reduce the computation effort of ATPG, test generation could be started earlier at higher abstraction level, which is in line with top-down design methodology that has become more popular nowadays. In this research, we employ Chen’s high-level fault model in the high-level ATPG. Besides shorter ATPG time as shown in many previous works, our study showed that high-level ATPG also contributes to test compaction. This is because most of the high-level faults correlate with the gate-level collapsed faults especially at input/output of the modules in a circuit. The high-level ATPG prototype used in our work is mainly composed by constraint-driven test generation engine and fault simulation engine. Experimental result showed that more reduced/compact test set can be generated from the high-level ATPG.
Highlights
The role of testing in integrated circuit (IC) is to determine the correctness of manufactured circuits
Besides shorter automatic test pattern generation (ATPG) time as shown in many previous works, our study showed that high-level ATPG contributes to test compaction
The test generation algorithms designed for the highlevel models are usually direct extensions of those for the gate-level models, in which the functional modules are treated as primitive components so fewer components are evaluated during test generation
Summary
The role of testing in integrated circuit (IC) is to determine the correctness of manufactured circuits. In order to cope with this situation, the top-down design methodology starting with highlevel description had been introduced. The test generation algorithms designed for the highlevel models are usually direct extensions of those for the gate-level models, in which the functional modules are treated as primitive components so fewer components are evaluated during test generation. Since digital design is first described at high-level, the test generation could be done earlier even before the design is synthesized into gate-level circuit. The resulting reduced structural complexity makes high-level test generation attractive. Functional test generation and functional fault simulation of a digital system described in high-level models offers an attractive alternative in test development
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