Abstract

In silicon insulated gate bipolar transistors, the trench gate structure is used to achieve smaller cell size and lower ON resistance, and thereby reduces energy loss. However, the thermal process can cause large stress near the trench and sometimes degrades device performance. This study proposed a three-dimensional model of a silicon chip with trench structures to analyze the stress distribution induced by thermal process around the trench, the scribe line, and the bottom surface of the chip. The calculated stress is in good agreement with measurement by Raman spectroscopy. The mesa top has much higher stress than the scribe line and the bottom surface. The stress depends on oxide thickness and the size scaling may reduce the stress.

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