Study on Channel Current Variation and Bias Stress Behavior of Fabricated a-Si:H TFTs with Wavy-Edge Source/Drain Electrodes

Abstract

We report the channel current variation and the bias stress behavior of hydrogenated amorphous silicon thinlm transistors (a-Si:H TFTs) that have wavy-edge source/drain (S/D) electrodes. Edge waviness of electrodes can be often observed in printed narrow lines. Wavy edges of the S/D electrodes were intentionally patterned by using photolithography to implement edge waviness of the printed electrodes. Based on the measured data, we found that the peak-to-peak magnitude of the S/D wavy edge was large and that the period of the wavy patterns and the phase-shift between the S/D wavy patterns had small e ects on TFT channel current variation. If a channel current variation of less than 10 % is to be guaranteed, the peak-to-peak magnitude of the S/D wavy edge need to be lower than 1 2 and 3 m for TFTs with channel lengths of 4 and 9 m, respectively. We also performed a bias stress test at room temperature for a set of TFTs having di erent peakto-peak magnitudes in the S/D wavy edges. Both constant voltage (linear region operation) and constant current (saturation region operation) stress conditions were used. The threshold voltage was more shifted for TFTs with larger peak-to-peak magnitude in the S/D wavy edges when TFTs were stressed in the constant current mode while almost the same amount of threshold voltage was shifted for TFTs having various peak-to-peak magnitudes when they were stressed in the constant voltage mode. The threshold voltage shift behavior was modeled with a power-law relationship and was explained by a non-uniform current distribution in the channel area and by an increase of e ective stress eld for the constant current stress mode.