Study of Total Ionizing Dose Effects in 65nm Digital Circuits with the DRAD Digital RADiation Test Chip

Abstract

Radiation damage to electronic components is one of the main concerns for LHC (Large Hadron Collider) on-detector ASIC design engineers. Studies are needed in order to achieve the radiation hardness required by the chips used in key sub-detectors of ATLAS and CMS upgrades. A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) on digital logic gates in a 65nm CMOS technology. Nine different versions of standard cell libraries are studied in this chip, basically differing in the device dimensions, $\text{V}_{\mathbf {t\, }}$flavor and layout of the device. Each library has eighteen test structures specifically designed to characterize delay degradation and power consumption of the standard cells. They are based on delay chains and ring oscillators with different gates, as well as specific test structures for the measurement of hold and setup time of sequential elements. Specific high speed structures (VCO and counters) are included for future high speed optical links chips. The test structures have been optimized and verified using 200 and 500 Mrad transistor models from the radiation working group of the RD53 collaboration. A test system has been developed for the DRAD chip to enable radiation tests to be performed in X-ray facilities. Results up to 1Grad under different conditions (temperature, bias and annealing) are reported.