Study of the Effects of Multibit Error Correction Codes on the Reliability of Memories in the Presence of MBUs

Abstract

Failures produced by soft errors in memories because of radiation or similar causes are an important problem due to the large impact that this issue has on the systems where they operate. There are several techniques that offer good results against single event upsets (SEUs), like single error correction-double error detection codes. However, there may be situations where these solutions are not enough, for example, when there is a large SEU arrival rate or multiple bit upsets (MBUs) are present. This last situation is becoming more frequent as technology scales, since in this case, the probability that a single event induces several errors in adjacent cells is higher. A possible solution to address this problem is the use of multibit protection codes, which are often utilized in other fields like communications. However, there are no developed models for memories that can put in perspective how these multibit protection codes behave in the presence of MBUs, and how the reliability of the system is affected by its use. In this paper, a reliability analysis of this case will be presented, studying how the proposed model behaves with respect to the traditional SEU ones and offering some applicability conditions. Both scenarios of memories with and without scrubbing will be analyzed, and several simulation results will be offered in order to prove the accuracy of the proposals.