Abstract

Cobalt salicide has been the reference salicide for sub −0.25 μm CMOS technology nodes to lower the sheet resistances on source, drain and poly areas. A critical step in the cobalt silicide formation is the Soft Sputter Etch (SSE) before Co deposition [A.H.M. Kamal, N.S. Argenti, C.S. Blair, IEEE Transaction on Semiconductor Manufacturing, vol. 15, No. 3, August 2002.]. It has to remove native oxide and impurities to ensure a clean surface, but it should also be soft enough to avoid leakages and resputtering. In this paper, the 300-mm SSE chamber behavior is analyzed on blanket and 90-nm technology node patterned wafers to explain the formation mechanism of defects observed in salicided areas. Defectivity has been observed along the spacers, especially in pinched active structures. A nitrogen analysis performed by μ-Auger spectroscopy showed that nitride from the spacers was re-sputtered on the active areas during the SSE process, subsequently blocking the salicidation. DOE on blanket wafers were run characterizing the 300-mm chamber behavior. No major differences were seen between 200- and 300-mm chambers on blanket wafers. Etch rate was found to be mainly dependent on the RF bias power, whereas both RF bias and RF coil powers influenced the DC bias voltage on the wafer during process. Furthermore, a DOE on 90-nm technology node patterned wafers was performed in order to reduce nitride resputtering and thereby improve defectivity and device performance. Results showed that optimizing the ratio between RF bias and RF coil and changing both RF values was a way to improve the salicidation process. Indeed, salicidation improvement can be achieved by rising the DC bias on the wafer.

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