Abstract
Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH2F2/CH4/O2/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO2. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.
Highlights
In order to overcome challenges such as short channel effect brought by scaling down metal-oxide-semiconductor field-effect transistors (MOSFETs), many new devices e.g., fin field effective transistors( FinFETs), tunneling field-effect transistors (TFETs), ultra-thin-body transistors (ULBTs) and gate-all-around nanowire transistors (GAA-NWTs) have been developed [1,2,3]
CtohnatcltuhseioSinNs on the end face of the nanosheet is totally etched while the SiN in the cavity remains Inner spacer for GAA nano-structure, low pressure chemical vapor deposition (LPCVD) silicon nitride has significantly better cavity filling effect than plasma enhanced chemical vapor deposition (PECVD)
The conventional inductively coupled plasma (ICP) etching tool and the optimized CH2F2/O2/CH4/Ar gas mixtures can control the silicon nitride inner spacer etching effect very well
Summary
In order to overcome challenges such as short channel effect brought by scaling down metal-oxide-semiconductor field-effect transistors (MOSFETs), many new devices e.g., fin field effective transistors( FinFETs), tunneling field-effect transistors (TFETs), ultra-thin-body transistors (ULBTs) and gate-all-around nanowire transistors (GAA-NWTs) have been developed [1,2,3]. Inner spacer was designed to reduce the parasitic capacitance between the gate and source/drain in stacked SiGe/Si structure GAA-NWTs [10,11]. The steps with challenges are SiGe cavity etching step and inner spacer formation with precise profile control and no damaging for the nanowires [12,13].
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