Study of potential high-k dielectric for UTB SOI MOSFETs using analytical modeling of the gate tunneling leakage

Abstract

In this paper, we use analytical models of the direct tunneling gate leakage current to determine the high-k dielectric suitable for the nanoscale ultra-thin body SOI MOSFET structure with the predicted equivalent oxide thickness (EOT) and the maximum value of gate leakage current according to the requirements of the latest ITRS roadmap for three technological nodes. The most important criteria for selecting alternative dielectrics (maximum gate leakage current, EOT, electron effective mass, dielectric constant k-value, barrier height and SiO2 thickness as an interfacial layer) were taken into account to determine the suitability of the gate oxide materials. In the ideal case without an interfacial layer, HfO2 and Lu2O3 were found to be the best gate oxide materials for the 17, 15 and 14 nm technological node requirements.