Study of parasitic oscillation of a multi-chip SiC MOSFET circuit based on a signal flow graph model by TCAD simulation

Abstract

This study presents a novel method to evaluate oscillation condition by technology computer-aided design (TCAD) simulation and is based on a signal flow graph model and a scattering parameter (S-parameter) computed using the TCAD simulation result. The parasitic oscillation of Silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) when a short circuit occurs has been investigated with the proposed method. The oscillation conditions of a circuit were computed with this technique and compared with those computed by TCAD transient simulation. The gate resistance to suppress oscillation is similar between these methods. Moreover, the method was also applied to estimate the stability of a circuit consisting of parallelly connected SiC MOSFETs. Two oscillation modes were taken into account. We demonstrated that the circuit parameters required to suppress parasitic oscillation can be computed using a simple calculation.