Abstract
The local electron power dissipation has been calculated in a field-effect nanowire transistor using a quantum transport formalism. Two different channel cross sections and optical and acoustic phonon mechanisms were considered. The phonon models used reproduce the phonon limited mobility in the cross sections studied. The power dissipation for different combinations of source, channel, and drain dimensions have been calculated. Due to the lack of complete electron energy relaxation inside the device, the Joule heat dissipation over-estimates the power dissipated in small nanotransistors. This over-estimation is larger for large cross sections due to the weaker phonon scattering. On the other hand, in narrow wires, the power dissipation inside the device can be large, therefore, mitigating against fabrication of very narrow nanowire transistors. We have also investigated the cooling of the device source region due to the mismatch of the Peltier coefficients between the source and the channel.
Highlights
N ANOWIRE field effect transistors are strong candidates for future CMOS technology due to superior electrostatic integrity [1], [2]
The corresponding percentage of Joule power dissipated inside the device and the current reduction are presented in table I for VG = 0.9 V
It will be shown that for the 6nm channel length device the channel is so short that much of the potential drop is concentrated in the channel/drain region where a substantial part of the power dissipation occurs but it is not as localized as predicted by the Joule power alone
Summary
N ANOWIRE field effect transistors are strong candidates for future CMOS technology due to superior electrostatic integrity [1], [2]. Power dissipation is one of the effects limiting aggressive transistor scaling. The study of power dissipation in extremely scaled nanowire transistors has not been investigated using the NEGF formalism. As the cross section of the transistor becomes small, the effective electron-phonon coupling increases and as a consequence the power dissipation increases [5]. We have used a NEGF formalism to study the relaxation of hot electrons for a gate-all-around Si nanowire transistor at high drain bias. Date of publication November 6, 2014; date of current version December 22, 2014.
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