Abstract
In this paper, we look into the reduction in leakage components of a fully depleted (FD) nanoscale double-gate (DG) MOSFET architecture. Here, we have developed an numerical model for PCHEM-DG MOSFET followed by the gate-controlled band-to-band tunneling leakage and gate leakage currents in the device of 10 nm gate length and observed the reduction in the leakage components over bulk-MOSFETs. Various leakage current components have been discussed and their variations with respect to bias and device parameters are presented. The results have been compared and contrasted with standard device simulator such as MINIMOS 6.0 for the purpose of validation of the results. A dramatic increase of the gate leakage and Band-to-Band Tunneling (BTBT) leakage in nanoscaled devices drastically increases total leakage power in a logic circuit. This device proposes to reduce this power dissipation. This work provides a simple and intuitive method for lowering of leakage currents which can be very salutary for the future nanoscale device technologies.
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