Abstract

In this article, we present a fast and cost-effective approach of fabricating laterally stacked nanostructures using a trench isolation technique. The essential part of this process is the patterning of sub-micrometer trenches onto the silicon substrate in a single lithographic step. The trenches are further tuned to make the channel length in the range of 100 nm, where the metallic electrodes are formed. An organic semiconductor (copper phthalocyanine, CuPc) is then selectively deposited onto the trenches by thermal evaporation method in order to successfully form a conducting channel. The current-voltage characteristics of such a nanostructure are also measured and analyzed.

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