Study of jitter generators for high-speed I/O interface jitter tolerance testing

Abstract

This paper proposes two low-cost jitter generators for high-speed I/O interface jitter tolerance testing. (i) The first one uses inter-symbol interference positively with digital control. The proposed circuit consists of mostly digital circuits with small amount of analog circuits (simple RC low-pass filter), and the digital part can be realized using FPGA or high-speed digital unit of an automated test equipment (ATE). (ii) The second one uses a digital AS modulator with some amount of analog circuits, and the digital part can be realized using high-speed digital unit of the ATE; the digital AS modulator can be realized by software on the ATE, and its output controls switches in the analog circuits. Their principles, theoretical analyses and simulation results are presented.