Abstract
The most recent technique for tuning proportional-integral-differential(PID) controllers is the Iterative Feedback Tuning (IFT) technique. The IFT has gone through many phases of improvement, such as increased transient performance, accelerated convergence, strengthened technique robustness and modified system stability. In this paper we propose the study of IFT technique in a view to create a novel hardware that implements IFT technique. To accomplish the said proposal, we carried out an overview of IFT technique basic theory and applications so that algorithm's expressions are refined to simplify development of hardware architecture. Then VHDL code is developed, simulated, and implemented on to the National Instruments (NI) Digital Electronics FPGA Board.
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