Study of gate source-drain overlap/gate-channel underlap in Heteojunction (50nm Ge channel) n-Double Gate TFET for different $\kappa$-spacer

Abstract

In this work a comparative study is performed between different gate source-drain overlap and gate channel underlap structures with conventional double gate tunnel field effect transistors (DGTFET) to overcome the challenges of scaling down of tunnel FET. To attain better ON current (I ON ), band-to-band tunneling (BTBT) and subthreshold swing (SS), low energy band gap material (Ge) is used in heterojunction n-type DGTFET. All device combinations are incorporated with various $\kappa$ -values of dielectric spacer in order to investigate the best switching ratio keeping the leakage current (I OFF ) into consideration for low power applications. It is observed that for n-type gate underlap tunnel FET, a high- $\kappa$ spacer with minimum length of 5 nm underlap provides best device performance. However, for a given spacer a large gate channel underlap or a gate source-drain overlap relatively lowers the device performance. Subthreshold swing provided by the 5 nm gate channel underlap n-DGTFET is recorded best as 13.93 mV/decade of 50 nm gate length. It also results maximum drain current (I ON ) as $1.13\times 10^{-4} \mathrm{A}/\mu\mathrm{m}$ for different $\kappa$ -values of dielectric spacer at supply voltage (V DS ) of 0.5 V.