Abstract

Amorphous tantalum pentoxide (Ta 2O 5) thin films on n-type Si substrates were prepared by d.c. magnetron reactive sputtering deposition technique. It was observed that the leakage current decreased with time when a voltage bias was first applied. The cause of this behavior was investigated using bias-temperature-stress test technique combined with the capacitance-voltage measurement with structures of Al/Ta 2O 5/Si metal-oxide-semiconductor (MOS) capacitors, and was identified to be owing to electron trapping in the Ta 2O 5 film and at the Ta 2O 5/Si interfaces. The current injection technique was further used to correlate the amount of charge trapped in the Ta 2O 5 with the leakage current passed through the Ta 2O 5 film, and it was found that most of the trapped electrons were located at the Ta 2O 5/Si interface. This electron trapping effect on the conduction mechanisms of the Ta 2O 5 films and the related reliability issues in dynamic random access memories applications are discussed.

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