Study of effect of gate-length downscaling on the analog/RF performance and linearity investigation of InAs-based nanowire Tunnel FET

Abstract

In this paper, we present a simulation study to report the effect of gate-length downscaling on the analog/RF performance and linearity investigation of InAs-based nanowire (NW) Tunnel FET (TFET). The different RF/analog and linearity figure of merits such as gm, RO, gm*RO, fT, fmax, GBW and 1-dB compression point of a NW TFET are extracted and the influence of gate-length downscaling on these parameters is analyzed. The RF/analog performance parameters obtained from InAs TFET is compared with an InAs MOSFET of identical dimension. Results reveal that superior RF and Linearity performance was obtained with gate-length downscaling for both devices under consideration. However, advantages of achieving improved RF performance with gate-length downscaling diminishes in terms of poor analog performance with gate-length downscaling for both the devices. This clearly indicates a trade-off between the analog and RF performance of a down-scaled InAs-based NW TFET and MOSFET. The results reveal that InAs TFET provides better fT, fmax and linearity performance in the saturation region than its MOSFET counterpart. It provides a reasonable RO, gm*RO at lower values of gate-overdrive voltage as compared to the InAs MOSFET. Therefore, this paper concludes that InAs NW TFETs have enormous potential to be a promising contender to the conventional bulk MOSFETs for realization of future generation low-power analog/RF applications.