Abstract
Tiling is a technique for extraction of parallelism which groups iterations of a nest of ‘for’ loops into blocks called tiles which can be scheduled for execution on the workstations connected by a network. Extraction of parallelism will be maximum when the workstations are busy in computation most of the time. Hence idle time of tiling is a very important parameter. In this paper we have presented results on the study of tiling transformation with respect to computation time and idle time. In our study we have considered tiles of rectangular shape and of size. N1 x N2.The iteration space can, however, be rectangular or parallelogram shaped and of size N1 x N2. The results presented in this paper can be used for tiling of iteration spaces such that idle time is minimum and can be easily integrated in a parallelising compiler. Modelling communication between workstations is important for tiling transformation. We have developed a new improved model for modelling communication between workstations.
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