Abstract
The tunneling field effect transistor is basically a gated p-i-n diode, is recently under rising interest due to its potential to deliver steep on-off slopes and its ability in operating at supply voltages below 0.5 V. We present simulation results of double gate pocket doped silicon n-channel Tunnel FET on the investigation of the influences of drain underlap. Ambipolar current behavior in details with gate-drain underlap is studied and it is observed that ambipolar current could be completely suppressed if 8-nm gate-drain underlap is used.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
