Study and Implementation of Low Power Decoder using DVL and TGL Logic

Abstract

This paper introduces the topologies involved in the designing of decoder of different size. Low power and high performance topologies for decoder are line decoding and mixed logic. Line decoding is a method in which non inverting decoder is designed using NOR gates and inverting decoder using NAND gates and higher order decoders are designed using 2–4 decoders as a pre decoders and universal gates. In mixed logic basic gates using dual value logic and transmission gate logic is discussed, these gates are helpful in implementation of 2–4 decoders, based on gate selection two decoders are designed first is non inverting decoder and second is inverting decoder. Two main topologies discussed first is for low power decoders that is focusing on minimum number of transistors and second is high performance decoders that is designed by using extra transistors where complimentary signal is transmitted. For higher order decoders mixed logic design has been used. The low power decoders are designed using low performance (LP) high order decoders and high performance high order decoders are designed using high performance (HP) decoders.