Abstract
Silicon detectors based on the HV-CMOS technology are being investigated as possible candidate for the outer layers of the ATLAS pixel detector for the High Luminosity LHC. In this framework the H35Demo ASIC has been produced in the 350 nm AMS technology (H35). The H35Demo chip has a large area (18.49 × 24.40 mm2) and includes four different pixel matrices and three test structures. In this paper the radiation hardness properties, in particular the evolution of the depletion region with fluence is studied using edge-TCT on test structures. Measurements on the test structures from chips with different substrate resistivity are shown for non irradiated and irradiated devices up to a cumulative fluence of 2 ⋅ 1015 1 MeV neq / cm2.
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