Abstract
Decoupled computer architectures attempt to achieve superscalar performance by exploiting the fine-grain parallelism between the data access and data execute tasks of a computer program. In this paper, we examine the major bottlenecks in the performance of decoupled architectures. These consist of the load unbalance between the access and execute processors, the limited access processor's instruction issue rate, and the memory bandwidth. We introduce a decoupled architecture that (1) eliminates the access processor's instruction issue bottleneck by reducing the number of data access instructions, and (2) reduces the effects of the memory bandwidth by allowing better data prefetching. The architecture employs special data access mechanisms that take advantage of the regularity of structure data's storage.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
