Abstract
Vertical thin film transistors (VTFTs) achieve sub-micron channel length without expensive high-resolution photolithography by taking advantage of a three-dimensional device structure. Recently, ZnO VTFTs with active layers deposited by spatial atomic layer deposition (SALD) were demonstrated with large current density (10 mA/mm), high mobility (>14 cm2/Vs) and large on-off ratio (>107) [1]. Asymmetric saturation-region current-voltage characteristics were also obtained when the transistor source and drain electrodes were interchanged. Using the Synopsys Sentaurus drift-diffusion simulator we developed a physics-based two-dimensional model for SALD ZnO VTFTs. Using the model, we are able to reproduce the electrical behavior of the ZnO VTFTs and understand the role of nanometer-scale features in the device structure.
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