Strong Single-Arm Latch Comparator with Reduced Power Consumption

Abstract

In today’s world, high speed comparators are used in analog to digital converters that measure and digitize the analogue signals. It is important to consider and optimize a variety of factors such as speed, delay, offset voltage and power consumption. To improve delay, area and power consumption a strong single-arm latch comparator is proposed here. It uses low threshold voltage transistors (LVT) for quick switching action, which reduces the delay. The conventional single tail comparator, existing strong arm latch comparator and proposed strong single-arm latch comparator are implemented using Cadence Virtuoso at 45 nm technology with supply voltage of 0.5 V. The rise and fall time of the proposed strong single-arm latch comparator are observed to be equal with the value of 15 ps, which makes it a symmetrical circuit. This is achieved using sizing of the MOSFETs. In the proposed strong single-arm latch comparator the i) overall speed is increased by 53.27% and 85.29% ii) delay is decreased by 30.75% and 45.96% iii) offset voltage is reduced by 58.11% and 23.6% practically and 11.11% and 8% theoretically iv) power consumption is decreased by 91.6% and 96.16% v) area is decreased by 97.37% and 94.15% in comparison with an existing strong arm latch comparator and conventional single tail comparator respectively.