Abstract
Technology of high-speed digitization of subnanosecond radio pulses, which is constructed via counting frame sampling, is discussed. The basis of the circuit architecture of the frame sampler involving the high-speed logic built around hyperfine complementary metal‒oxide‒semiconductor structures, as well as the basis of the array of picosecond delay lines, is formulated. It is demonstrated that the strobe-frame-sampling technology excludes high-frequency clocking and, consequently, minimizes the circuit power consumption and ensures picosecond time resolution of a recovered signal, corresponding to a sampling rate of up to 100 G sample/s implemented in practice. The software model of the frame sampler making it possible to investigate and parametrically synthesize the circuit topology of high-speed digital devices is developed in the Simulink environment.
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