Stress-sensitive properties of silicon-gate MOS devices

Abstract

Stress-sensitive properties were measured on both p- and n-channel silicongate MOS devices fabricated on (100) Si at room temperature. Stress-induced variations in drain currents for both enhancement- and depletion-mode MOS transistors with various channel-dopings were measured over a wide range of gate biases. In addition to piezoresistance effect, remarkable drain-current variations were observed at weak-inversion and explained theoretically in terms of changes in minority carrier densities due to energy band shifts by stresses. Elastoresistance shear-constants for polycrystalline-silicon gate layers were also obtained and compared with coefficients for source-drain diffused layers. Further, the elastoresistance of p-type polycrystalline-silicon films was investigated on doping-concentration dependences. A theoretical model for polycrystalline-silicon elastoresistance was developed based on the barrier model for conductivity in polycrystalline-silicon. Results obtained from the model were compared with the experimental results and found to be in good agreement at higher doping-concentrations than trap density.