Stress-induced voiding in aluminum and copper interconnects

Abstract

Stress-induced voiding (SIV) is a serious reliability problem in metal interconnects. For aluminum a phenomenological model was developed which allows the extrapolation of metallization life times from stress conditions to operation conditions of the integrated circuit. Resistance drift measurements during high-temperature storage (HTS) on wafer-level have been performed and the experimental data could be fitted with that model. The influences of different parameters such as line width, metal level, thermal anneals of certain metal levels during processing and the deposition temperature of the interlevel dielectric material on the SIV behavior are discussed. The SIV behavior of copper dual damascene metallizations has been investigated on via line structures. A linear resistance drift during high-temperature storage has been observed. This is in contrast to aluminum, where a non-linear behavior was found. Failure analysis showed voids inside the via and not in the metal line as it has been observed in aluminum. Stress simulations have been performed in order to explain this behavior. Due to the complex stress state in a copper dual damascene via the temperature dependence of SIV in copper is different from that of aluminum.