Stress Technology Impact on Device Performances and Reliability for Sub-90 nm Silicon-on-Insulator Complementary Metal–Oxide–Semiconductor Field-Effect-Transistors

Abstract

In this work, we investigated the thickness effect of a high-stress gate capping layer (GC layer) on <100> 90 nm partially-depleted silicon-on-insulator complementary metal–oxide–semiconductor field-effect transistor (PD-SOI CMOSFETs). Additionally, we inspected the hot-carrier reliability on body-contacted (BC) SOI devices with various thicknesses of the GC layer (1100 and 700 Å) and a conventional SiN layer (CN layer). For nMOSFETs, devices with an 1100 Å GC layer possess worse characteristics and hot-carrier degradations than devices with a 700 Å GC layer in terms of excess high tensile stress. For pMOSFETs, the GC layer only slightly affects device performance, but seriously affects hot-carrier-induced device degradation. Therefore, the thickness of this high-stress GC layer should be optimized to improve the device performance.