Stress monitoring in flip chip packaging process

Abstract

Residual stress is commonly generated during the packaging process, and may heavily affect the electrical performance of the devices in silicon chips. Finding out the stress distribution and the relationship between packaging process and inducement of stress, can help us improve the packaging process, and figure out potential causes of the chip failure. In this study, a series of experiments are performed to monitor the stress variation when the test chips are in the packaging process. Both the stress during and after packaging process are measured and recorded. Compared to the residual strain measured after each packaging process, the stress variation monitored during the process shows a more intuitive result. The flip chip bonding process leads to about 350 MPa normal stress to the test chip, while the shear stress is relatively small. Underfill curing process induces about 100 MPa normal stress, and stress increase heavily when temperature rises up. The accelerated life tests are performed to examine the reliability of the package, and the stress variation is also monitored by the stress senor test chips. The stress of the chip without underfill shows a steady decrease as the number of cycling increase, while the stress of the chip with underfill do not show any regular change.