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Abstract
Stress-induced performance change in electron packaging architecture is a major concern when the keep-out zone (KOZ) and corresponding integration density of interconnect systems and transistor devices are considered. In this study, a finite element analysis (FEA)-based submodeling approach is demonstrated to analyze the stress-affected zone of through-silicon via (TSV) and its influences on a planar metal oxide semiconductor field transistor (MOSFET) device. The feasibility of the widely adopted analytical solution for TSV stress-affected zone estimation, Lamé radial stress solution, is investigated and compared with the FEA-based submodeling approach. Analytic results reveal that the Lamé stress solution overestimates the TSV-induced stress in the concerned device by over 50%, and the difference in the estimated results of device performance between Lamé stress solution and FEA simulation can reach 22%. Moreover, a silicon–germanium-based lattice mismatch stressor is designed in a silicon p-type MOSFET, and its effects are analyzed and compared with those of TSV residual stress. The S/D stressor dominates the stress status of the device channel. The demonstrated FEA-based submodeling approach is effective in analyzing the stress impact from packaging and device-level components and estimating the KOZ issue in advanced electronic packaging.
Highlights
Moore’s law has been adopted for half a century, and it is still regarded as the target of transistor device performance
From the viewpoint of the piezoresistance of Si pMOSFET, the stress sensitivity in the vertical direction of the device channel is at least 13 times lower than those in the longitudinal and transverse directions [10]
The estimated longitudinal by the stress buffer behavior of the barrier and shallow trench isolation (STI) structure between the Through-silicon via (TSV) core and Si stress introduced into the device channel provided by Equations (1) and (3) is 353.95 and pMOSFET
Summary
Moore’s law has been adopted for half a century, and it is still regarded as the target of transistor device performance. Silicon (Si) is the mainstream material for current semiconductor technology because of its low cost, mature fabrication process and acceptable performance. Through-silicon via (TSV) is the main interconnect architecture in 3D integrated circuit packaging, and the current mainstream TSV is fabricated with electroplated copper (Cu) [6,7,8,9,10,11]. The protrusion and thermal stress of TSV generally depend on the fabrication and annealing procedure and can generate cohesive and interfacial cracking on TSV [12,13,14,15,16]. In the fabrication procedure of Cu TSV, the annealing process is a critical step to manage the material characteristics, residual stress and Cu pumping.
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