Stress control during thermal annealing of copper interconnects

Abstract

Grain growth of Cu interconnects in an ultralow k dielectric was achieved at an elevated anneal temperature of 300 °C without stress voiding related problems. For this, a TaN metal passivation layer was deposited on the Cu interconnect surface prior to the thermal annealing process, which suppressed void formation within the Cu features during the anneal process and reduced inelastic deformation within the interconnects after cooling down to room temperature. As compared to the conventional anneal process at 100 °C, the passivation layer enabled further Cu grain growth at elevated temperatures, which then resulted in lower electrical resistance in the Cu interconnects.